URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 247

Rev	Log message	Author	Age	Path
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5103d 15h	/openrisc/trunk/or1ksim/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5104d 15h	/openrisc/trunk/or1ksim/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5104d 16h	/openrisc/trunk/or1ksim/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5105d 15h	/openrisc/trunk/or1ksim/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5106d 16h	/openrisc/trunk/or1ksim/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5108d 15h	/openrisc/trunk/or1ksim/
106	Removing old tests, pending addition of new ones.	jeremybennett	5108d 16h	/openrisc/trunk/or1ksim/
104	Candidate release 0.4.0rc4	jeremybennett	5111d 23h	/openrisc/trunk/or1ksim/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5120d 17h	/openrisc/trunk/or1ksim/
100	Single precision FPU stuff for or1ksim	julius	5120d 19h	/openrisc/trunk/or1ksim/