URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 435

Rev	Log message	Author	Age	Path
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5057d 22h	/openrisc/trunk/or1ksim/
224	Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg.	jeremybennett	5058d 05h	/openrisc/trunk/or1ksim/
220	Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this.	jeremybennett	5064d 21h	/openrisc/trunk/or1ksim/
202	Adding executed log in binary format capability to or1ksim	julius	5071d 01h	/openrisc/trunk/or1ksim/
144	Missing file to fix bug 1797.	jeremybennett	5088d 00h	/openrisc/trunk/or1ksim/
143	Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195).	jeremybennett	5088d 01h	/openrisc/trunk/or1ksim/
134	Updates for stable release 0.4.0	jeremybennett	5096d 05h	/openrisc/trunk/or1ksim/
127	New config option to allow l.xori with unsigned operand.	jeremybennett	5102d 01h	/openrisc/trunk/or1ksim/
124	Overflow handling now in line with architecture manual. Tests added.	jeremybennett	5102d 21h	/openrisc/trunk/or1ksim/
123	Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added.	jeremybennett	5103d 01h	/openrisc/trunk/or1ksim/