OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 568

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
440 Updated documentation to describe new Ethernet usage. jeremybennett 4927d 21h /openrisc/trunk/or1ksim/
437 Or1ksim - ethernet peripheral update, working much better. julius 4935d 15h /openrisc/trunk/or1ksim/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4936d 16h /openrisc/trunk/or1ksim/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4939d 22h /openrisc/trunk/or1ksim/
433 New single program interrupt test programs. jeremybennett 4941d 00h /openrisc/trunk/or1ksim/
432 Updates to handle interrupts correctly. jeremybennett 4941d 01h /openrisc/trunk/or1ksim/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4943d 22h /openrisc/trunk/or1ksim/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 4944d 01h /openrisc/trunk/or1ksim/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4946d 21h /openrisc/trunk/or1ksim/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4955d 02h /openrisc/trunk/or1ksim/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.