OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cache/] - Rev 855

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5124d 18h /openrisc/trunk/or1ksim/cache/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5130d 19h /openrisc/trunk/or1ksim/cache/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5145d 01h /openrisc/trunk/or1ksim/cache/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5146d 03h /openrisc/trunk/or1ksim/cache/
91 Tidy up of some obsolete configuration code. jeremybennett 5158d 16h /openrisc/trunk/or1ksim/cache/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5158d 17h /openrisc/trunk/or1ksim/cache/
83 Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. jeremybennett 5159d 15h /openrisc/trunk/or1ksim/cache/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5159d 16h /openrisc/trunk/or1ksim/cache/
80 Add missing configuration files to SVN. jeremybennett 5159d 20h /openrisc/trunk/or1ksim/cache/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5490d 01h /openrisc/trunk/or1ksim/cache/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.