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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 370

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Rev Log message Author Age Path
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5129d 20h /openrisc/trunk/or1ksim/cpu/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5129d 21h /openrisc/trunk/or1ksim/cpu/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5130d 20h /openrisc/trunk/or1ksim/cpu/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5133d 21h /openrisc/trunk/or1ksim/cpu/
104 Candidate release 0.4.0rc4 jeremybennett 5137d 04h /openrisc/trunk/or1ksim/cpu/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5145d 22h /openrisc/trunk/or1ksim/cpu/
100 Single precision FPU stuff for or1ksim julius 5146d 00h /openrisc/trunk/or1ksim/cpu/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5151d 23h /openrisc/trunk/or1ksim/cpu/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5166d 05h /openrisc/trunk/or1ksim/cpu/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5167d 07h /openrisc/trunk/or1ksim/cpu/

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