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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 391

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Rev	Log message	Author	Age	Path
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5170d 21h	/openrisc/trunk/or1ksim/cpu/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5171d 20h	/openrisc/trunk/or1ksim/cpu/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5171d 21h	/openrisc/trunk/or1ksim/cpu/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5172d 20h	/openrisc/trunk/or1ksim/cpu/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5175d 21h	/openrisc/trunk/or1ksim/cpu/
104	Candidate release 0.4.0rc4	jeremybennett	5179d 04h	/openrisc/trunk/or1ksim/cpu/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5187d 22h	/openrisc/trunk/or1ksim/cpu/
100	Single precision FPU stuff for or1ksim	julius	5188d 00h	/openrisc/trunk/or1ksim/cpu/
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5193d 23h	/openrisc/trunk/or1ksim/cpu/
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5208d 05h	/openrisc/trunk/or1ksim/cpu/

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