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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 472

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Rev Log message Author Age Path
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5101d 18h /openrisc/trunk/or1ksim/cpu/
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5102d 02h /openrisc/trunk/or1ksim/cpu/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5108d 17h /openrisc/trunk/or1ksim/cpu/
202 Adding executed log in binary format capability to or1ksim julius 5114d 21h /openrisc/trunk/or1ksim/cpu/
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5131d 22h /openrisc/trunk/or1ksim/cpu/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5145d 22h /openrisc/trunk/or1ksim/cpu/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5146d 18h /openrisc/trunk/or1ksim/cpu/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5146d 22h /openrisc/trunk/or1ksim/cpu/
122 Added l.ror and l.rori with associated tests. jeremybennett 5147d 18h /openrisc/trunk/or1ksim/cpu/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5147d 18h /openrisc/trunk/or1ksim/cpu/

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