URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] - Rev 475

Rev	Log message	Author	Age	Path
202	Adding executed log in binary format capability to or1ksim	julius	5134d 12h	/openrisc/trunk/or1ksim/cpu/or32/
143	Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195).	jeremybennett	5151d 13h	/openrisc/trunk/or1ksim/cpu/or32/
127	New config option to allow l.xori with unsigned operand.	jeremybennett	5165d 13h	/openrisc/trunk/or1ksim/cpu/or32/
124	Overflow handling now in line with architecture manual. Tests added.	jeremybennett	5166d 09h	/openrisc/trunk/or1ksim/cpu/or32/
123	Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added.	jeremybennett	5166d 13h	/openrisc/trunk/or1ksim/cpu/or32/
122	Added l.ror and l.rori with associated tests.	jeremybennett	5167d 09h	/openrisc/trunk/or1ksim/cpu/or32/
121	Adds exception handling to l.jalr and l.jr. Adds appropriate tests.	jeremybennett	5167d 10h	/openrisc/trunk/or1ksim/cpu/or32/
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5168d 06h	/openrisc/trunk/or1ksim/cpu/or32/
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5170d 10h	/openrisc/trunk/or1ksim/cpu/or32/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5171d 09h	/openrisc/trunk/or1ksim/cpu/or32/