OpenCores

URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] - Rev 385

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5182d 05h	/openrisc/trunk/or1ksim/cpu/or32/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5183d 04h	/openrisc/trunk/or1ksim/cpu/or32/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5186d 05h	/openrisc/trunk/or1ksim/cpu/or32/
104	Candidate release 0.4.0rc4	jeremybennett	5189d 12h	/openrisc/trunk/or1ksim/cpu/or32/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5198d 06h	/openrisc/trunk/or1ksim/cpu/or32/
100	Single precision FPU stuff for or1ksim	julius	5198d 08h	/openrisc/trunk/or1ksim/cpu/or32/
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5204d 07h	/openrisc/trunk/or1ksim/cpu/or32/
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5218d 13h	/openrisc/trunk/or1ksim/cpu/or32/
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5219d 15h	/openrisc/trunk/or1ksim/cpu/or32/
91	Tidy up of some obsolete configuration code.	jeremybennett	5232d 04h	/openrisc/trunk/or1ksim/cpu/or32/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.