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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] - Rev 518

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Rev	Log message	Author	Age	Path
220	Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this.	jeremybennett	5106d 20h	/openrisc/trunk/or1ksim/cpu/or32/
202	Adding executed log in binary format capability to or1ksim	julius	5113d 00h	/openrisc/trunk/or1ksim/cpu/or32/
143	Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195).	jeremybennett	5130d 01h	/openrisc/trunk/or1ksim/cpu/or32/
127	New config option to allow l.xori with unsigned operand.	jeremybennett	5144d 01h	/openrisc/trunk/or1ksim/cpu/or32/
124	Overflow handling now in line with architecture manual. Tests added.	jeremybennett	5144d 21h	/openrisc/trunk/or1ksim/cpu/or32/
123	Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added.	jeremybennett	5145d 01h	/openrisc/trunk/or1ksim/cpu/or32/
122	Added l.ror and l.rori with associated tests.	jeremybennett	5145d 21h	/openrisc/trunk/or1ksim/cpu/or32/
121	Adds exception handling to l.jalr and l.jr. Adds appropriate tests.	jeremybennett	5145d 21h	/openrisc/trunk/or1ksim/cpu/or32/
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5146d 18h	/openrisc/trunk/or1ksim/cpu/or32/
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5148d 21h	/openrisc/trunk/or1ksim/cpu/or32/

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