OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [debug/] - Rev 842

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5108d 02h /openrisc/trunk/or1ksim/debug/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5123d 22h /openrisc/trunk/or1ksim/debug/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5124d 19h /openrisc/trunk/or1ksim/debug/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5144d 00h /openrisc/trunk/or1ksim/debug/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5150d 01h /openrisc/trunk/or1ksim/debug/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5164d 07h /openrisc/trunk/or1ksim/debug/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5165d 09h /openrisc/trunk/or1ksim/debug/
91 Tidy up of some obsolete configuration code. jeremybennett 5177d 22h /openrisc/trunk/or1ksim/debug/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5177d 23h /openrisc/trunk/or1ksim/debug/
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5178d 07h /openrisc/trunk/or1ksim/debug/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.