OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [debug/] - Rev 460

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5195d 05h /openrisc/trunk/or1ksim/debug/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5209d 11h /openrisc/trunk/or1ksim/debug/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5210d 12h /openrisc/trunk/or1ksim/debug/
91 Tidy up of some obsolete configuration code. jeremybennett 5223d 01h /openrisc/trunk/or1ksim/debug/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5223d 02h /openrisc/trunk/or1ksim/debug/
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5223d 10h /openrisc/trunk/or1ksim/debug/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5224d 01h /openrisc/trunk/or1ksim/debug/
80 Add missing configuration files to SVN. jeremybennett 5224d 05h /openrisc/trunk/or1ksim/debug/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5554d 11h /openrisc/trunk/or1ksim/debug/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.