URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] - Rev 402

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5144d 05h	/openrisc/trunk/or1ksim/doc/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5145d 07h	/openrisc/trunk/or1ksim/doc/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5147d 06h	/openrisc/trunk/or1ksim/doc/
104	Candidate release 0.4.0rc4	jeremybennett	5150d 13h	/openrisc/trunk/or1ksim/doc/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5159d 07h	/openrisc/trunk/or1ksim/doc/
100	Single precision FPU stuff for or1ksim	julius	5159d 09h	/openrisc/trunk/or1ksim/doc/
99	Bug in test evaluation for library fixed.	jeremybennett	5164d 07h	/openrisc/trunk/or1ksim/doc/
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5165d 08h	/openrisc/trunk/or1ksim/doc/
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5179d 14h	/openrisc/trunk/or1ksim/doc/
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5180d 16h	/openrisc/trunk/or1ksim/doc/