URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] - Rev 240

Rev	Log message	Author	Age	Path
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5137d 20h	/openrisc/trunk/or1ksim/doc/
104	Candidate release 0.4.0rc4	jeremybennett	5141d 04h	/openrisc/trunk/or1ksim/doc/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5149d 22h	/openrisc/trunk/or1ksim/doc/
100	Single precision FPU stuff for or1ksim	julius	5150d 00h	/openrisc/trunk/or1ksim/doc/
99	Bug in test evaluation for library fixed.	jeremybennett	5154d 22h	/openrisc/trunk/or1ksim/doc/
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5155d 23h	/openrisc/trunk/or1ksim/doc/
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5170d 05h	/openrisc/trunk/or1ksim/doc/
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5171d 06h	/openrisc/trunk/or1ksim/doc/
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5176d 21h	/openrisc/trunk/or1ksim/doc/
91	Tidy up of some obsolete configuration code.	jeremybennett	5183d 19h	/openrisc/trunk/or1ksim/doc/