URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 353

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5322d 02h	/openrisc/trunk/orpsocv2/
56	adding generic pll model to orpsoc	julius	5330d 04h	/openrisc/trunk/orpsocv2/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5332d 18h	/openrisc/trunk/orpsocv2/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5343d 01h	/openrisc/trunk/orpsocv2/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5361d 02h	/openrisc/trunk/orpsocv2/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5361d 22h	/openrisc/trunk/orpsocv2/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5376d 00h	/openrisc/trunk/orpsocv2/
50	Adding or32_funcs.S	julius	5376d 04h	/openrisc/trunk/orpsocv2/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5394d 18h	/openrisc/trunk/orpsocv2/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5410d 05h	/openrisc/trunk/orpsocv2/