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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 409

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Rev Log message Author Age Path
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5021d 16h /openrisc/trunk/orpsocv2/
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5021d 18h /openrisc/trunk/orpsocv2/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5022d 16h /openrisc/trunk/orpsocv2/
350 Adding new OR1200 processor to ORPSoCv2 julius 5022d 20h /openrisc/trunk/orpsocv2/
349 ORPSoCv2 update with new software and makefile update julius 5022d 20h /openrisc/trunk/orpsocv2/
348 First stage of ORPSoCv2 update - more to come julius 5022d 20h /openrisc/trunk/orpsocv2/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5080d 18h /openrisc/trunk/orpsocv2/
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5112d 20h /openrisc/trunk/orpsocv2/
78 Fixed typo in Silos workaround script rherveille 5175d 15h /openrisc/trunk/orpsocv2/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5175d 15h /openrisc/trunk/orpsocv2/

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