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Rev Log message Author Age Path
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4973d 00h /openrisc/trunk/orpsocv2/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4973d 12h /openrisc/trunk/orpsocv2/
410 ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again.		 julius 4974d 11h /openrisc/trunk/orpsocv2/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4974d 12h /openrisc/trunk/orpsocv2/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4975d 00h /openrisc/trunk/orpsocv2/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4976d 05h /openrisc/trunk/orpsocv2/
398 ORPSoCv2 removing generic backend path - not needed julius 4977d 12h /openrisc/trunk/orpsocv2/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4978d 11h /openrisc/trunk/orpsocv2/
396 ORPSoCv2 final software fixes...for now. See updated README julius 4981d 10h /openrisc/trunk/orpsocv2/
395 ORPSoCv2 moving ethernet tests to correct place julius 4981d 10h /openrisc/trunk/orpsocv2/

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