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Rev Log message Author Age Path
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4906d 19h /openrisc/trunk/orpsocv2/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4907d 03h /openrisc/trunk/orpsocv2/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4907d 20h /openrisc/trunk/orpsocv2/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4907d 23h /openrisc/trunk/orpsocv2/
470 ORPSoC OR1200 crt0 updates. julius 4911d 23h /openrisc/trunk/orpsocv2/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4913d 00h /openrisc/trunk/orpsocv2/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4914d 03h /openrisc/trunk/orpsocv2/
465 ORPSoC SPI flash load Makefile and README updates. julius 4914d 17h /openrisc/trunk/orpsocv2/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4915d 02h /openrisc/trunk/orpsocv2/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4926d 19h /openrisc/trunk/orpsocv2/

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