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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 542

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Rev Log message Author Age Path
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4874d 23h /openrisc/trunk/orpsocv2/
487 ORPSoC main software makefile update julius 4877d 21h /openrisc/trunk/orpsocv2/
486 ORPSoC updates, mainly software, i2c driver julius 4877d 21h /openrisc/trunk/orpsocv2/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4882d 01h /openrisc/trunk/orpsocv2/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4899d 06h /openrisc/trunk/orpsocv2/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4900d 05h /openrisc/trunk/orpsocv2/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4901d 21h /openrisc/trunk/orpsocv2/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4902d 05h /openrisc/trunk/orpsocv2/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4902d 22h /openrisc/trunk/orpsocv2/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4903d 01h /openrisc/trunk/orpsocv2/

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