OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 627

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4776d 09h /openrisc/trunk/orpsocv2/
528 ORPSoC SPI flash programming link script bug fix julius 4781d 09h /openrisc/trunk/orpsocv2/
506 ORPSoC or1200 interrupt and syscall generation test julius 4802d 03h /openrisc/trunk/orpsocv2/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement		 julius 4802d 04h /openrisc/trunk/orpsocv2/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4819d 00h /openrisc/trunk/orpsocv2/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4819d 20h /openrisc/trunk/orpsocv2/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4822d 00h /openrisc/trunk/orpsocv2/
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default		 julius 4823d 00h /openrisc/trunk/orpsocv2/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4823d 03h /openrisc/trunk/orpsocv2/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4823d 20h /openrisc/trunk/orpsocv2/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.