URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 414

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5368d 16h	/openrisc/trunk/orpsocv2/bench/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5369d 12h	/openrisc/trunk/orpsocv2/bench/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5383d 14h	/openrisc/trunk/orpsocv2/bench/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5402d 08h	/openrisc/trunk/orpsocv2/bench/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5417d 19h	/openrisc/trunk/orpsocv2/bench/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5453d 18h	/openrisc/trunk/orpsocv2/bench/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5493d 12h	/openrisc/trunk/orpsocv2/bench/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5497d 19h	/openrisc/trunk/orpsocv2/bench/
6	Checking in ORPSoCv2	julius	5516d 07h	/openrisc/trunk/orpsocv2/bench/