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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 492

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Rev Log message Author Age Path
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5030d 19h /openrisc/trunk/orpsocv2/bench/
348 First stage of ORPSoCv2 update - more to come julius 5030d 23h /openrisc/trunk/orpsocv2/bench/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5231d 08h /openrisc/trunk/orpsocv2/bench/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5231d 09h /openrisc/trunk/orpsocv2/bench/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5234d 03h /openrisc/trunk/orpsocv2/bench/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5254d 02h /openrisc/trunk/orpsocv2/bench/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5258d 08h /openrisc/trunk/orpsocv2/bench/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5261d 03h /openrisc/trunk/orpsocv2/bench/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5271d 00h /openrisc/trunk/orpsocv2/bench/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5318d 00h /openrisc/trunk/orpsocv2/bench/

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