URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 362

Rev	Log message	Author	Age	Path
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5420d 21h	/openrisc/trunk/orpsocv2/bench/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5456d 20h	/openrisc/trunk/orpsocv2/bench/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5496d 14h	/openrisc/trunk/orpsocv2/bench/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5500d 20h	/openrisc/trunk/orpsocv2/bench/
6	Checking in ORPSoCv2	julius	5519d 08h	/openrisc/trunk/orpsocv2/bench/