URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 862

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5363d 08h	/openrisc/trunk/orpsocv2/bench/sysc/src/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5382d 02h	/openrisc/trunk/orpsocv2/bench/sysc/src/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5433d 13h	/openrisc/trunk/orpsocv2/bench/sysc/src/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5473d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/
6	Checking in ORPSoCv2	julius	5496d 01h	/openrisc/trunk/orpsocv2/bench/sysc/src/