URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] - Rev 530

Rev	Log message	Author	Age	Path
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4962d 02h	/openrisc/trunk/orpsocv2/boards/
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	4962d 14h	/openrisc/trunk/orpsocv2/boards/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	4963d 14h	/openrisc/trunk/orpsocv2/boards/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4964d 02h	/openrisc/trunk/orpsocv2/boards/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5017d 09h	/openrisc/trunk/orpsocv2/boards/
71	ORPSoC board builds, adding readmes	julius	5216d 18h	/openrisc/trunk/orpsocv2/boards/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5221d 00h	/openrisc/trunk/orpsocv2/boards/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5223d 18h	/openrisc/trunk/orpsocv2/boards/