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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] - Rev 807

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Rev Log message Author Age Path
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4839d 13h /openrisc/trunk/orpsocv2/boards/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4840d 06h /openrisc/trunk/orpsocv2/boards/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4842d 17h /openrisc/trunk/orpsocv2/boards/
492 ORPSoC VPI interface for modelsim and documentation update julius 4856d 17h /openrisc/trunk/orpsocv2/boards/
486 ORPSoC updates, mainly software, i2c driver julius 4869d 15h /openrisc/trunk/orpsocv2/boards/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4873d 19h /openrisc/trunk/orpsocv2/boards/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4890d 23h /openrisc/trunk/orpsocv2/boards/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4891d 23h /openrisc/trunk/orpsocv2/boards/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4893d 15h /openrisc/trunk/orpsocv2/boards/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4894d 18h /openrisc/trunk/orpsocv2/boards/

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