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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] - Rev 854

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Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4838d 02h /openrisc/trunk/orpsocv2/boards/xilinx/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4840d 12h /openrisc/trunk/orpsocv2/boards/xilinx/
492 ORPSoC VPI interface for modelsim and documentation update julius 4854d 12h /openrisc/trunk/orpsocv2/boards/xilinx/
486 ORPSoC updates, mainly software, i2c driver julius 4867d 10h /openrisc/trunk/orpsocv2/boards/xilinx/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4871d 15h /openrisc/trunk/orpsocv2/boards/xilinx/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4888d 19h /openrisc/trunk/orpsocv2/boards/xilinx/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4889d 18h /openrisc/trunk/orpsocv2/boards/xilinx/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4891d 10h /openrisc/trunk/orpsocv2/boards/xilinx/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4892d 14h /openrisc/trunk/orpsocv2/boards/xilinx/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4897d 15h /openrisc/trunk/orpsocv2/boards/xilinx/

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