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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 528

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Rev Log message Author Age Path
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4981d 17h /openrisc/trunk/orpsocv2/rtl/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4982d 05h /openrisc/trunk/orpsocv2/rtl/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4983d 11h /openrisc/trunk/orpsocv2/rtl/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4985d 16h /openrisc/trunk/orpsocv2/rtl/
392 ORPSoCv2 software path reorganisation stage 1. julius 4989d 08h /openrisc/trunk/orpsocv2/rtl/
391 Removing modules no longer needed in ORPSoCv2 julius 4990d 08h /openrisc/trunk/orpsocv2/rtl/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5021d 15h /openrisc/trunk/orpsocv2/rtl/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5033d 12h /openrisc/trunk/orpsocv2/rtl/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5033d 22h /openrisc/trunk/orpsocv2/rtl/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5035d 07h /openrisc/trunk/orpsocv2/rtl/

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