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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 540

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Rev Log message Author Age Path
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4999d 13h /openrisc/trunk/orpsocv2/rtl/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5003d 02h /openrisc/trunk/orpsocv2/rtl/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 5003d 14h /openrisc/trunk/orpsocv2/rtl/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 5004d 14h /openrisc/trunk/orpsocv2/rtl/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5005d 03h /openrisc/trunk/orpsocv2/rtl/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5006d 08h /openrisc/trunk/orpsocv2/rtl/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5008d 14h /openrisc/trunk/orpsocv2/rtl/
392 ORPSoCv2 software path reorganisation stage 1. julius 5012d 05h /openrisc/trunk/orpsocv2/rtl/
391 Removing modules no longer needed in ORPSoCv2 julius 5013d 06h /openrisc/trunk/orpsocv2/rtl/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5044d 12h /openrisc/trunk/orpsocv2/rtl/

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