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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 568

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Rev Log message Author Age Path
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4898d 17h /openrisc/trunk/orpsocv2/rtl/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4918d 16h /openrisc/trunk/orpsocv2/rtl/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4925d 07h /openrisc/trunk/orpsocv2/rtl/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 4938d 07h /openrisc/trunk/orpsocv2/rtl/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 4946d 17h /openrisc/trunk/orpsocv2/rtl/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4950d 06h /openrisc/trunk/orpsocv2/rtl/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.
julius 4950d 18h /openrisc/trunk/orpsocv2/rtl/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.
julius 4951d 18h /openrisc/trunk/orpsocv2/rtl/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4952d 06h /openrisc/trunk/orpsocv2/rtl/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4953d 12h /openrisc/trunk/orpsocv2/rtl/

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