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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 415

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Rev Log message Author Age Path
348 First stage of ORPSoCv2 update - more to come julius 5032d 07h /openrisc/trunk/orpsocv2/rtl/verilog/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5090d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5232d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5235d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5259d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5272d 08h /openrisc/trunk/orpsocv2/rtl/verilog/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5314d 04h /openrisc/trunk/orpsocv2/rtl/verilog/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5319d 08h /openrisc/trunk/orpsocv2/rtl/verilog/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5330d 00h /openrisc/trunk/orpsocv2/rtl/verilog/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5340d 08h /openrisc/trunk/orpsocv2/rtl/verilog/

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