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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 504

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Rev Log message Author Age Path
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4967d 08h /openrisc/trunk/orpsocv2/rtl/verilog/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4969d 13h /openrisc/trunk/orpsocv2/rtl/verilog/
392 ORPSoCv2 software path reorganisation stage 1. julius 4973d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
391 Removing modules no longer needed in ORPSoCv2 julius 4974d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5005d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5017d 09h /openrisc/trunk/orpsocv2/rtl/verilog/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5017d 19h /openrisc/trunk/orpsocv2/rtl/verilog/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5019d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
361 OPRSoCv2 - adding things left out in last check-in julius 5019d 09h /openrisc/trunk/orpsocv2/rtl/verilog/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5019d 09h /openrisc/trunk/orpsocv2/rtl/verilog/

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