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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 788

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Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4833d 07h /openrisc/trunk/orpsocv2/rtl/verilog/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4866d 20h /openrisc/trunk/orpsocv2/rtl/verilog/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4884d 23h /openrisc/trunk/orpsocv2/rtl/verilog/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4886d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4886d 23h /openrisc/trunk/orpsocv2/rtl/verilog/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4887d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4894d 22h /openrisc/trunk/orpsocv2/rtl/verilog/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4906d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4926d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4933d 05h /openrisc/trunk/orpsocv2/rtl/verilog/

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