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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] - Rev 805

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Rev Log message Author Age Path
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4915d 17h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4942d 07h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4955d 07h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4963d 17h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4967d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4967d 18h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4970d 12h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5020d 14h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5020d 23h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5022d 14h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/

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