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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] - Rev 814

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Rev Log message Author Age Path
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4888d 09h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4895d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4907d 08h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4933d 22h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4946d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4955d 07h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4958d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4959d 09h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4962d 03h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5012d 04h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/

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