OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] - Rev 853

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4842d 08h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4875d 20h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4894d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4895d 16h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4896d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4896d 17h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4903d 23h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4915d 16h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4942d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4955d 05h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.