URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 368

Rev	Log message	Author	Age	Path
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5338d 22h	/openrisc/trunk/orpsocv2/sim/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5356d 23h	/openrisc/trunk/orpsocv2/sim/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5371d 21h	/openrisc/trunk/orpsocv2/sim/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5390d 15h	/openrisc/trunk/orpsocv2/sim/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5442d 01h	/openrisc/trunk/orpsocv2/sim/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5465d 22h	/openrisc/trunk/orpsocv2/sim/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5481d 19h	/openrisc/trunk/orpsocv2/sim/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5486d 02h	/openrisc/trunk/orpsocv2/sim/
36	Better clean rule in makefile	julius	5500d 02h	/openrisc/trunk/orpsocv2/sim/
6	Checking in ORPSoCv2	julius	5504d 14h	/openrisc/trunk/orpsocv2/sim/