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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 403

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Rev Log message Author Age Path
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5312d 02h /openrisc/trunk/orpsocv2/sim/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5317d 06h /openrisc/trunk/orpsocv2/sim/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5327d 22h /openrisc/trunk/orpsocv2/sim/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5338d 05h /openrisc/trunk/orpsocv2/sim/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5356d 06h /openrisc/trunk/orpsocv2/sim/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5371d 04h /openrisc/trunk/orpsocv2/sim/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5389d 22h /openrisc/trunk/orpsocv2/sim/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5441d 09h /openrisc/trunk/orpsocv2/sim/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5465d 06h /openrisc/trunk/orpsocv2/sim/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5481d 03h /openrisc/trunk/orpsocv2/sim/

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