OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 492

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5193d 16h /openrisc/trunk/orpsocv2/sim/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5194d 15h /openrisc/trunk/orpsocv2/sim/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5241d 06h /openrisc/trunk/orpsocv2/sim/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5241d 07h /openrisc/trunk/orpsocv2/sim/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5243d 22h /openrisc/trunk/orpsocv2/sim/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5244d 01h /openrisc/trunk/orpsocv2/sim/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5263d 23h /openrisc/trunk/orpsocv2/sim/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5271d 00h /openrisc/trunk/orpsocv2/sim/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5280d 22h /openrisc/trunk/orpsocv2/sim/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5322d 17h /openrisc/trunk/orpsocv2/sim/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.