URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 501

Rev	Log message	Author	Age	Path
348	First stage of ORPSoCv2 update - more to come	julius	5056d 19h	/openrisc/trunk/orpsocv2/sim/
78	Fixed typo in Silos workaround script	rherveille	5209d 14h	/openrisc/trunk/orpsocv2/sim/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5209d 15h	/openrisc/trunk/orpsocv2/sim/
76	Added: +libext+.v Added: +incdir+.	rherveille	5210d 14h	/openrisc/trunk/orpsocv2/sim/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5257d 05h	/openrisc/trunk/orpsocv2/sim/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5257d 05h	/openrisc/trunk/orpsocv2/sim/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5259d 21h	/openrisc/trunk/orpsocv2/sim/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5260d 00h	/openrisc/trunk/orpsocv2/sim/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5279d 22h	/openrisc/trunk/orpsocv2/sim/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5286d 23h	/openrisc/trunk/orpsocv2/sim/