URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 363

Rev	Log message	Author	Age	Path
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5330d 15h	/openrisc/trunk/orpsocv2/sim/bin/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5348d 16h	/openrisc/trunk/orpsocv2/sim/bin/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5363d 14h	/openrisc/trunk/orpsocv2/sim/bin/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5382d 08h	/openrisc/trunk/orpsocv2/sim/bin/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5433d 18h	/openrisc/trunk/orpsocv2/sim/bin/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5457d 15h	/openrisc/trunk/orpsocv2/sim/bin/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5473d 12h	/openrisc/trunk/orpsocv2/sim/bin/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5477d 19h	/openrisc/trunk/orpsocv2/sim/bin/
36	Better clean rule in makefile	julius	5491d 19h	/openrisc/trunk/orpsocv2/sim/bin/
6	Checking in ORPSoCv2	julius	5496d 07h	/openrisc/trunk/orpsocv2/sim/bin/