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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 462

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Rev Log message Author Age Path
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5008d 14h /openrisc/trunk/orpsocv2/sw/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5020d 22h /openrisc/trunk/orpsocv2/sw/
361 OPRSoCv2 - adding things left out in last check-in julius 5022d 12h /openrisc/trunk/orpsocv2/sw/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5022d 12h /openrisc/trunk/orpsocv2/sw/
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5022d 21h /openrisc/trunk/orpsocv2/sw/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5023d 06h /openrisc/trunk/orpsocv2/sw/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5024d 12h /openrisc/trunk/orpsocv2/sw/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5025d 12h /openrisc/trunk/orpsocv2/sw/
349 ORPSoCv2 update with new software and makefile update julius 5025d 16h /openrisc/trunk/orpsocv2/sw/
348 First stage of ORPSoCv2 update - more to come julius 5025d 16h /openrisc/trunk/orpsocv2/sw/

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