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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 661

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Rev Log message Author Age Path
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4905d 22h /openrisc/trunk/orpsocv2/sw/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4907d 21h /openrisc/trunk/orpsocv2/sw/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4908d 17h /openrisc/trunk/orpsocv2/sw/
470 ORPSoC OR1200 crt0 updates. julius 4912d 17h /openrisc/trunk/orpsocv2/sw/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4913d 18h /openrisc/trunk/orpsocv2/sw/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4914d 22h /openrisc/trunk/orpsocv2/sw/
465 ORPSoC SPI flash load Makefile and README updates. julius 4915d 12h /openrisc/trunk/orpsocv2/sw/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4915d 20h /openrisc/trunk/orpsocv2/sw/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4940d 08h /openrisc/trunk/orpsocv2/sw/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4947d 12h /openrisc/trunk/orpsocv2/sw/

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