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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 794

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Rev Log message Author Age Path
487 ORPSoC main software makefile update julius 4869d 17h /openrisc/trunk/orpsocv2/sw/
486 ORPSoC updates, mainly software, i2c driver julius 4869d 17h /openrisc/trunk/orpsocv2/sw/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4873d 21h /openrisc/trunk/orpsocv2/sw/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4892d 01h /openrisc/trunk/orpsocv2/sw/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4894d 01h /openrisc/trunk/orpsocv2/sw/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4894d 21h /openrisc/trunk/orpsocv2/sw/
470 ORPSoC OR1200 crt0 updates. julius 4898d 21h /openrisc/trunk/orpsocv2/sw/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4899d 22h /openrisc/trunk/orpsocv2/sw/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4901d 01h /openrisc/trunk/orpsocv2/sw/
465 ORPSoC SPI flash load Makefile and README updates. julius 4901d 15h /openrisc/trunk/orpsocv2/sw/

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