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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 854

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Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4837d 17h /openrisc/trunk/orpsocv2/sw/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4840d 04h /openrisc/trunk/orpsocv2/sw/
489 ORPSoC sw cleanup. Remove warnings. julius 4864d 03h /openrisc/trunk/orpsocv2/sw/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4864d 04h /openrisc/trunk/orpsocv2/sw/
487 ORPSoC main software makefile update julius 4867d 01h /openrisc/trunk/orpsocv2/sw/
486 ORPSoC updates, mainly software, i2c driver julius 4867d 01h /openrisc/trunk/orpsocv2/sw/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4871d 06h /openrisc/trunk/orpsocv2/sw/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4889d 10h /openrisc/trunk/orpsocv2/sw/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4891d 10h /openrisc/trunk/orpsocv2/sw/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4892d 05h /openrisc/trunk/orpsocv2/sw/

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