URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] - Rev 508

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5003d 15h	/openrisc/trunk/orpsocv2/sw/tests/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5004d 15h	/openrisc/trunk/orpsocv2/sw/tests/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5005d 03h	/openrisc/trunk/orpsocv2/sw/tests/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5006d 09h	/openrisc/trunk/orpsocv2/sw/tests/
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	5008d 15h	/openrisc/trunk/orpsocv2/sw/tests/
395	ORPSoCv2 moving ethernet tests to correct place	julius	5011d 14h	/openrisc/trunk/orpsocv2/sw/tests/
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5011d 14h	/openrisc/trunk/orpsocv2/sw/tests/