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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] - Rev 561

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Rev Log message Author Age Path
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4981d 09h /openrisc/trunk/orpsocv2/sw/tests/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4984d 23h /openrisc/trunk/orpsocv2/sw/tests/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4985d 11h /openrisc/trunk/orpsocv2/sw/tests/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4986d 11h /openrisc/trunk/orpsocv2/sw/tests/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4986d 23h /openrisc/trunk/orpsocv2/sw/tests/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4988d 05h /openrisc/trunk/orpsocv2/sw/tests/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4990d 10h /openrisc/trunk/orpsocv2/sw/tests/
395 ORPSoCv2 moving ethernet tests to correct place julius 4993d 10h /openrisc/trunk/orpsocv2/sw/tests/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4993d 10h /openrisc/trunk/orpsocv2/sw/tests/

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