URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] - Rev 870

Rev	Log message	Author	Age	Path
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8212d 05h	/or1k/branches/branch_qmem/or1200/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8215d 23h	/or1k/branches/branch_qmem/or1200/
596	SR[TEE] should be zero after reset.	lampret	8216d 03h	/or1k/branches/branch_qmem/or1200/
595	Fixed 'the NPC single-step fix'.	lampret	8216d 22h	/or1k/branches/branch_qmem/or1200/
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8217d 05h	/or1k/branches/branch_qmem/or1200/
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8220d 06h	/or1k/branches/branch_qmem/or1200/
571	Changed alignment exception EPCR. Not tested yet.	lampret	8220d 15h	/or1k/branches/branch_qmem/or1200/
570	Fixed order of syscall and range exceptions.	lampret	8220d 18h	/or1k/branches/branch_qmem/or1200/
569	Default ASIC configuration does not sample WB inputs.	lampret	8221d 03h	/or1k/branches/branch_qmem/or1200/
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8221d 06h	/or1k/branches/branch_qmem/or1200/