URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] - Rev 1006

Rev	Log message	Author	Age	Path
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8005d 04h	/or1k/branches/stable_0_1_x/
984	Disable SB until it is tested	lampret	8005d 05h	/or1k/branches/stable_0_1_x/
983	First checkin	lampret	8005d 06h	/or1k/branches/stable_0_1_x/
982	Moved to sim/bin	lampret	8005d 06h	/or1k/branches/stable_0_1_x/
981	First checkin.	lampret	8005d 07h	/or1k/branches/stable_0_1_x/
980	Removed sim.tcl that shouldn't be here.	lampret	8005d 07h	/or1k/branches/stable_0_1_x/
979	Removed old test case binaries.	lampret	8005d 07h	/or1k/branches/stable_0_1_x/
978	Added variable delay for SRAM.	lampret	8005d 07h	/or1k/branches/stable_0_1_x/
977	Added store buffer.	lampret	8005d 07h	/or1k/branches/stable_0_1_x/
976	Added store buffer	lampret	8005d 07h	/or1k/branches/stable_0_1_x/