URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] - Rev 1765

Rev	Log message	Author	Age	Path
1543	Try to find a symbolic name of the location where we crashed	nogj	6915d 11h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1542	Print stackdump to stderr instead of stdout	nogj	6915d 11h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1540	* Breakup the tick_job function into smaller ones. * Fix lots of conner cases. * Add tests for the tick timer.	nogj	6915d 11h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1539	Speed up the dmmu	nogj	6916d 00h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1538	Speed up the immu	nogj	6916d 00h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1537	Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr	nogj	6916d 00h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1532	Add pretty spr dumping code	nogj	6919d 11h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1531	Remove non-trigerable out-of-range checks	nogj	6919d 11h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1529	* The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu. * Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR.	nogj	6920d 13h	/or1k/branches/stable_0_2_x/or1ksim/cpu/
1527	Fix the execution log when an mtspr instruction causes an itlb miss	nogj	6920d 19h	/or1k/branches/stable_0_2_x/or1ksim/cpu/